Commercial microprocessors currently operate on clock signals in the gigahertz range. The scale of today's VLSI designs requires the designs to account for clock skew. Clock skew is the relative difference in time that the clock signal reaches different parts of the integrated circuit. In a microprocessor, for example, a global clock signal must be distributed to different parts of the chip. This internal clock signal must be distributed to a large number of clock pins. As clock frequencies increase, the skew can be a limiting factor. With increasing clock frequency, the clock skew caused by many nondeterministic factors such as process variations, supply voltage fluctuation and temperature gradient consumes a significant portion of clock period. For high performance synchronous circuitry, the design of a robust global clock distribution system which can sustain various parameter variations becomes an increasingly difficult and time-consuming task.
As a result, reducing clock skew is a goal in the art. RC shunted networks have been successfully used to reduce the clock skew under process variations. Three wide spine shunts have been proposed to reduce the skew between the leaf nodes of a very deep driver tree. See, e.g., N. A. Kurd, et al, “A Multigigahertz Clocking Scheme for the Pentium® 4 Microprocessor,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, November 2001 pp. 1647-53. Others have proposed a clock mesh driven by balanced H-tree for global clock distribution. See, e.g., M. Orshansky, L. Milor, P. Chen, K. Keutzer and C. Hu, Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuit, IEEE trans. on CAD, p. 544-553, vol. 21, No. 5, May 2002.
However, when the clock frequency increases to multi-giga hertz range, the inductance effect of the shunt wires becomes significant. Clock meshes are used in the industry to reduce skew. Clock meshes form an RC wire network. The inductance effect of the RC network is ignored at clock frequencies of present commercial chips, e.g., the 4 GHz Pentium 4. However, the trend is toward higher clock frequencies at which the inductance effect can no longer be ignored. Additionally, for example, at a 10 GHz clock rate, the time of flight between two corners of a chip is comparable to the clock cycle. The RC model of the shunt effect is not valid at such frequencies. The inductance of the shunt can even cause worse skew.
Active circuits have been proposed to address clock skew. Particular examples include the following. Phase detectors and coupled oscillators have been proposed with shunts of less than a quarter wavelength to lock the oscillators together. See, Galton et al, “Clock Distribution Using Coupled Oscillators,” Proc. of ISCAS 1996, vol. 3, pp. 217-220. Active feedback with phase detectors and distributed phase locked loops have also been proposed. Gutnik and Chandraksan, “Active GHz Clock Network Using Distributed PLLs,” IEEE Journal of Solid-State Circuits, pp. 1553-1560, vol. 35, No. 11, November 2000. Combined clock generation and distribution using standing wave oscillators has been proposed. O'Mahony et al. “Design of a 10 GHz Clock Distribution Network Using Coupled Standing-Wave Oscillators,” Proc. of DAC, pp. 682-687, June 2003. This work distributes sine waves, as opposed to the conventional approach of distributing square waves. However, the distribution scheme of O'Mahony et al. does not use a global clock source. Instead, clocks are generating locally and distributed. Wood, et al., “Rotary Traveling-Wave Oscillator Arrays: A New Clock Technology” IEEE JSSC, pp. 1654-1665, November 2001. The use of active components may be successful to overcome clock skew at high clock frequencies. Compared to a passive scheme, though, the active component approach raises stability issues and, in some cases, may be more sensitive to process variations during fabrication.